1. Field of the Invention
The present invention relates generally to semiconductor fabrication and, more particularly, to systems and methods for controlling the effective dielectric constant of materials used in a semiconductor device.
2. Description of Related Art
Semiconductor fabrication involves two separate processes. First, devices are created on a wafer surface. Then, those devices are connected to each other using various metal layers in a process called interconnect metallization. One or more layers of dielectric material provide the necessary isolation between metal layers. The dielectric material may be, for example, silicon oxide, silicon nitride, or the like. Once the dielectric is deposited over a metal layer, it is etched in masking step to create vias or plugs, which are openings that expose the underlying metal layer. The vias or plugs are then filled with conductive material.
Although necessary to isolate the various metal layers, dielectric layers present significant challenges to the operation of high-performance circuits. Particularly, the combination of metal resistance and dielectric capacitance slows down the transmission of electric signals within the circuit. Further, dielectric capacitance is directly proportional to the dielectric constant (k) of the material used. Generally speaking, low-k materials are preferable when fabricating faster circuits. However, the inventor hereof has recognized that low-k materials are typically porous, have poor strength characteristics, and are more susceptible to damage, thus compromising their reliability.
These referenced shortcomings are not intended to be exhaustive, but rather are among many recognized by the present inventor that tend to impair the effectiveness of previously known techniques; however, those mentioned here are sufficient to demonstrate that the methodologies appearing in the art have not been satisfactory and that a significant need exists for the techniques described and claimed in this disclosure.